1. Field of the Invention
The present invention relates to an inductor recognition method, a layout inspection method, a computer readable recording medium in which a layout inspection program is recorded and a process for a semiconductor device and, in particular, to an inductor recognition method and a layout inspection method used in a CAD (computer-aided design) tool for the design and verification step of a layout of a circuit in the development of a semiconductor device and to a computer readable recording medium which records a layout inspection program which carries out the above layout inspection method as well as to a process for a semiconductor device utilizing the layout inspection program.
2. Description of the Background Art
Conventionally, in the development and production steps of LSIs (large scale integrated circuits), after carrying out the logic design step of LSI circuits and the logic verification step of the circuits, the layout design and verification step is carried out to determine the layout of elements, interconnections, and the like, formed on the semiconductor substrates in order to produce LSIs which realize the circuit diagram of the designed circuit. In this layout design and verification step, a verification is carried out to see if the layout of the elements, interconnections, or the like, precisely reflect the circuit diagram and if the interconnection width and the distance between interconnections satisfy the design standard. Such a verification task is carried out by using a CAD tool (program for a verification) which is usually referred to as an LVS (layout versus schematic) tool or a DRC (design rule check) tool. Such a CAD tool is utilized by using a computer wherein, for example, a CAD tool program, which is a program for a layout inspection, is installed.
By using such a CAD tool it becomes possible, at the time of developing and producing a semiconductor device, which includes a number of circuit elements such as an LSI, to verify whether or not the circuit diagram is precisely reflected and whether or not the design standard is satisfied. Then, at present, where the integrity of LSIs, or the like, have increased and miniaturization has advanced, the verification of the layout by the naked eye has become virtually impossible and a CAD tool, as described above, has become an essential tool in the development and production steps of a semiconductor device.
In a conventional CAD tool, however, inductors in a circuit are not particularly recognized so as to be treated in the same manner as a conventional interconnection though interconnections and field effect transistors are, respectively, recognized in the layout so that the verification of the design standard, or the like, are carried out. Therefore, as for inductors, inspection is carried out by the naked eye to see if they match the circuit diagram and to see if they satisfy the design standard. This is because the integrity of a semiconductor device which includes inductors is not, conventionally, great and the number of inductors, such as coils, included in one semiconductor device circuit is not great, so that it is entirely possible to carry out the inspection by the naked eye.
In recent years, however, together with the advance in miniaturization and increase in integration of semiconductor devices, the increase in integration of semiconductor devices (for example, system LSIs) which include an RF circuit using inductors, or the like, has progressed so that the number of elements formed in one system LSI has increased. In such a system LSI the number of inductors in the circuit has increased so that a large amount of time and labor has been needed for verifying these inductors by the naked eye. Therefore, the step of verification of inductors has become one of the causes which makes the development step of a system LSI take a long period of time. In addition, since the verification is carried out by the naked eye it is considered that the risk of occurrence of verification failure becomes high in comparison with the case where the verification of the design standard, or the like, is automatically carried out by a CAD tool.
The purpose of this invention is to provide an inductor recognition method for recognizing an inductor in the layout of a semiconductor device, a layout inspection method which allows the carrying out of an automatic verification of the design standard, or the like, in an inductor by utilizing this inductor recognition method and a process for a semiconductor device using this layout inspection method.
An inductor recognition method according to one aspect of this invention includes the step of arranging an inductor position representation mark which surrounds the design pattern of an interconnection part working as an inductor and having a starting point and a finishing point; the step of arranging a starting point position representation mark and a finishing point position representation mark so as to surround, respectively, regions corresponding to the starting point and the finishing point in the design pattern; and the step of recognizing information with respect to the inductor to be designed by means of the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark.
In this manner, coordinate information of the region where an inductor exists can be detected by means of the inductor position representation mark and a design pattern of an interconnection part, which works as an inductor, placed between the starting point position representation mark and the finishing point position representation mark inside of the inductor position representation mark can be distinguished from the other design patterns of the interconnection part. Therefore, the design pattern of the interconnection part placed between the starting point position representation mark and the finishing point position representation mark can be detected as the design pattern of the inductor. As a result of this, as for the design pattern of the interconnection part which works as an inductor, it becomes possible to automatically carry out, in the same manner as with other interconnection circuit elements, the verification of the coordination with the circuit diagram and to carry out the inspection step in order to see if the characteristic value, as an inductor, becomes the same as the set value.
A layout inspection method according to another aspect of this invention is a layout inspection method of a semiconductor device including the step of arranging an inductor position representation mark which surrounds a design pattern of an interconnection part working as an inductor and having a starting point and a finishing point; the step of arranging a starting point position representation mark and a finishing point position representation mark so as to surround, respectively, regions corresponding to the starting point and the finishing point in the design pattern; the step of recognizing information with respect to the inductor to be designed by means of the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark; the step of calculating a characteristic evaluation value of the inductor based on information with respect to the inductor; and the step of comparing the characteristic evaluation value with the reference value of the characteristic evaluation value.
In this manner, coordinate information of a region wherein an inductor exists can be detected by means of the inductor position representation mark and the design pattern of the interconnection part placed between the starting point position representation mark and the finishing point position representation mark inside of the inductor position representation mark can be distinguished from other design patterns of the interconnection part. Therefore, the design pattern of the interconnection part placed between the starting point position representation mark and the finishing point position representation mark can be detected as the design pattern of the inductor. In addition, in the case that the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark are allocated, the calculation of the characteristic evaluation value of the inductor and the comparison of this calculated characteristic evaluation value with the reference value can be carried out so that whether or not the inductor to be designed satisfies predetermined characteristics can be judged quickly and easily.
In the above described layout inspection method according to another aspect, it is preferable for the step of calculating the characteristic evaluation value to include the step of gaining structure information of the inductor, based on the information with respect to the inductor, and the step of calculating the characteristic evaluation value using the structure information.
In this case, when information with respect to the inductor, such as coordinate data of the interconnection part which forms the inductor, is used, the structure information, such as the length or width of the interconnection part, which forms the inductor, can be easily gained. Such structure information is data necessary for calculating the characteristic evaluation value, such as the inductance or the Q value of the inductor.
In the above described layout inspection method according to another aspect, the structure information may be the size information of the inductor.
In this case, the size information of the inductor can be utilized as basic data for calculating the inductance or the Q value of the inductor as the characteristic evaluation value. Accordingly, it becomes possible to automatically calculate the inductance or the Q value of the inductor.
In the above described layout inspection method according to another aspect, the structure information may be information of the number of windings of the inductor.
In this case, since the information of the number of windings of the inductor can be utilized as basic data for calculating the inductance or the Q value of the inductor, it becomes possible to automatically calculate the inductance or the Q value of the inductor.
In the above described layout inspection method according to another aspect, the structure information may be the information of the interconnection width of the interconnection which forms the inductor.
In this case, the above information of the interconnection width can be utilized as basic data for calculating the parasitic capacitance, the parasitic resistance and, moreover, the Q value of the inductor as the characteristic evaluation values.
In the above described layout inspection method according to another aspect, the structure information may be coordinate data with respect to holes exposing the interconnection part and connecting the interconnection part to another interconnection part.
In this case, the above coordinate data with respect to holes can be utilized as basic data for calculating the parasitic capacitance, the parasitic resistance and, moreover, the Q value of the inductor as the characteristic evaluation values.
In the above described layout inspection method according to another aspect, the structure information may be size information and number information of holes exposing the interconnection part and connecting the interconnection part to another interconnection part.
In this case, the above size information and number information of holes can be utilized as basic data for calculating the parasitic capacitance, the parasitic resistance and, moreover, the Q value of the inductor as the characteristic evaluation values.
In the above described layout inspection method according to another aspect, the structure information may be information with respect to materials of the interconnection, of which the inductor is formed.
In this case, since the information with respect to the material of the interconnection, of which the inductor is formed, can be utilized as basic data for calculating the inductance or the Q value of the inductor, it becomes possible to automatically calculate the inductance or the Q value of the inductor.
In the above described layout inspection method according to another aspect, it is preferable for the characteristic evaluation values to include, at least, one of the values from among the group consisting of the inductance, the parasitic capacitance, the parasitic resistance and the Q value of the inductor.
In this case, by using the above described data as the characteristic evaluation values, the characteristics of the inductor can be precisely evaluated.
A process for a semiconductor device according to still another aspect of this invention uses the above described layout inspection method according to another aspect.
In this case, by utilizing the above described layout inspection method according to another aspect, the layout verification of the inductor, which is conventionally carried out by the naked eye, can be automated using a CAD tool, or the like. As a result of this, the period of time for the development and process for the semiconductor device can be reduced and the precision in the layout verification of the inductor can be increased.
A computer readable recording medium according to a still further aspect of this invention records a layout inspection program for allowing a computer to carry out the step of arranging an inductor position representation mark which surrounds a design pattern of an interconnection part, which works as an inductor and which has a starting point and a finishing point; the step of arranging a starting point position representation mark and a finishing point position representation mark so as to surround, respectively, regions corresponding to the starting point and the finishing point in the design pattern; and the step of recognizing information with respect to the inductor to be designed by means of the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark.
In this case, according to the above described recording medium, the coordinate information of the region where the inductor exists can be detected by means of the inductor position representation mark and the design pattern of the interconnection part, which is placed between the starting point position representation mark and the finishing point position representation mark inside of the inductor position representation mark and which works as an inductor, can be distinguished from the design pattern of other interconnection parts. Therefore, it becomes possible to automatically detect the design pattern of the interconnection part placed between the starting point position representation mark and the finishing point position representation mark as the design pattern of the inductor.
The above described layout inspection program recorded in the computer readable recording medium according to a still further aspect may further allow a computer to implement the step of calculating the characteristic evaluation value of the inductor based on the information with respect to the inductor; and the step of comparing the characteristic evaluation value with the reference value of the characteristic evaluation value.
In this case, according to the above described recording medium, the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark are arranged and, thereby, the calculation of the characteristic evaluation value of the inductor and the comparison of this calculated characteristic evaluation value with the reference value can be carried out so that whether or not the inductor to be designed satisfies predetermined characteristics can be quickly and easily determined.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.